Responsibilities
1. Implement verification for block level, subsystem and SoC level designs using advance verification methodologies to meet quality and schedule goals
2. Work with system architects and RTL designers to develop verification requirements and test plans based on specifications
3. Analyse and debug simulation failures
4. Create, track, and close bugs in bug tracking tool
5. Analyse code coverage and functional coverage reports
6. Regression analysis
7. Develop, maintain and publish verification specifications
8. Gate level simulations
Qualifications
9. BSEE/BSc (MEng prefered) as well as at least 9 years relevant work experience
10. Fluent in System Verilog UVM and SVA
11. Excellent debugging and problem-solving skills
12. Familiarity with Metric Driven Verification methodology
13. Experience in writing test plans and creating directed and random test cases
14. Scripting skills Python, Perl, shell etc.
15. Working knowledge of Linux operating system
16. Embedded C experience considered an advantage
17. Experience with Synopsys tool suite an advantage
18. Preferably knowledge of AMBA and wired/wireless protocols
19. Excellent written and oral communication skills
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