Senior Digital Design Engineer We’re looking for a Senior ASIC Digital Design EngineerExperience required
* RTL Design with system Verilog
* Linting checks with spyglass
* STA
* Synthesis
* Experience with formal verification would be a plus
Key Qualifications
* BS/MS degree with a minimum of 8years of related experience.
* Proficient in scripting languages (Python, Tcl Perl, unix shell)
* Familiar with RTL best design practices with SystemVerilog
* Familiar with implementation and verification front end flows
* Strong communication skills
#J-18808-Ljbffr