FEOL (Front-End-Of-Line) Process Integration Development Engineer
Job Details:
Job Description:
Fab Sort Manufacturing is responsible for producing all Intel silicon using advanced manufacturing processes in facilities across Arizona, Ireland, Israel, and Oregon. In alignment with Intel's IDM2.0 strategy, Fab Sort Manufacturing is expanding operations to meet the demands of both internal and foundry customers, introducing state-of-the-art technologies into high-volume manufacturing.
This job seeks Front-End-Of-Line (FEOL) Process Integration engineers for Intel's HVM Global Yield organization. Selected candidates will collaborate with FEOL integration members, Global Yield teams, fab modules, and Technology Development team members to optimize processes and achieve yield ramp-up in the early production stage, supporting both internal and external customers.
FEOL Integration Development Engineers are responsible for leading engineering projects to execute high-volume manufacturing yield roadmaps, collaborating with Technology Development and Local Yield teams, working with FEOL/BEOL Integration, Device, Defect Reduction, and Yield Analysis teams, conducting feasibility studies, managing New Product Introductions, partnering with Local Yield teams, and improving product yield, quality, performance, and reducing wafer costs.
Key Responsibilities:
* Leading engineering projects to execute high-volume manufacturing yield roadmaps and achieving performance targets.
* Collaborating with Technology Development and Local Yield teams to implement new technologies in production fabs.
* Working with FEOL/BEOL Integration, Device, Defect Reduction, and Yield Analysis teams to identify root causes of yield and performance issues and executing mitigation plans within set timelines.
* Conducting feasibility studies and experiments to characterize processes and enhance product performance throughout development.
* Managing New Product Introductions (NPI) in production fabs and optimizing processes to meet foundry customer specifications.
* Partnering with Local Yield teams to improve product yield, quality, performance, and reduce wafer costs.
Qualifications:
Minimum Qualifications:
* Bachelor's degree in a relevant science or engineering field, with at least 4 years of experience.
* Experience in advanced node semiconductor industry, specifically in FEOL Process Integration; level of experience will influence job grade.
* Proficient understanding of Device Physics, with experience in FinFET or Gate-All-Around technology development or high-volume manufacturing.
* Familiarity with module processes such as lithography, dry etch, wet etch, CMP, diffusion, implant, thin films, and metrology.
* Strong problem-solving skills, self-initiative, and ability to learn independently.
* Ability to collaborate effectively with multi-functional and multi-cultural teams.
* Excellent communication skills.
Preferred Qualifications:
* Advanced degree (Master's or Ph.D.) in Electrical Engineering, Physics, or Materials Science; related fields may be considered based on industry experience.
* Experience in project/program management and/or as a TFT lead.
* Strong interpersonal skills, including the ability to influence and motivate others.
* Experience engaging with external foundry customers through technical interactions.
* Familiarity with GAA (Gate-All-Around) technology architecture.
* Background in new semiconductor technology development.
Job Type:
Experienced Hire
Shift:
Shift 1 (Ireland)
Primary Location:
Ireland, Leixlip
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Work Model for this Role:
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.