Job Title: UVM Verification Engineer
We are seeking a skilled ASIC Verification Engineer to contribute towards the design, integration and verification of new IP products for high speed communications on a contract basis.
This is a 6-7 month initial contract with the possibility of renewal. The role will be remote based in Ireland, with an immediate start available.
The successful engineer will require knowledge and experience in the following areas:
* ASIC design and verification expertise
* Strong background in RTL design using Verilog
* Verification skills in SystemVerilog and UVM
* Familiarity with high speed interfaces and designs such as SERDES, PCIe, USB, SATA etc.
For this position, the ideal candidate will possess a solid understanding of hardware description languages (HDLs) and digital logic design principles.
A thorough knowledge of verification methodologies, tools, and best practices will also be beneficial in ensuring the quality and reliability of the designed components.
In addition, the ability to work independently and collaboratively within a team environment will be essential in meeting project deadlines and deliverables.
If you have a strong passion for designing and verifying complex digital systems, and are eager to join a dynamic team, we encourage you to apply for this exciting opportunity.