Job Summary
This role requires a Senior Staff Verification Engineer to work with design, firmware and hardware emulation teams to ensure the verification of proprietary power devices for performance, completeness and correctness.
Key Responsibilities
* Develop architecture for verification environments at block, subsystem and SoC level designs.
* Create UVM-SV Scoreboards for self-checking regressions.
* Design Functional Coverage items like Covergroups and Corverpoints as part of Metric Driven Verification Environments.
* Develop SystemVerilog Assertions for use in Simulation Environments.
* Define and manage Verification Plans (vPlans) using Cadence vManager tools.
* Create Automated Regression Environments.
* Verify analog, digital and firmware functions, as well as evaluate and benchmark full system performance.
* Collaborate with analog designers, digital designers, systems architecture, firmware, applications and test engineering to specify, design, develop and manage a verification system for SOC.
* Knowledge of protocol interfaces for spec compliance (PMBus, SVI, SVID, I2C, AHB etc.).
* Track and report project progress against key milestones.
* Establish an environment that fosters collaboration, effective communication and learning.
Requirements
* PhD, post-graduate or degree qualification in Electronic Engineering or similar.
* 10+ years' relevant engineering experience.
* Experience with full-product verification flows, including HW & FW.
* Familiarity with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodology.
* Experience with Assertions like System Verilog Assertions.
* Knowledge of vManager, vPlan and Regressions.
* Extensive usage of RTL simulation tools.
* UVM, System Verilog, Perl/Python shell-scripting skills required.
* Excellent interpersonal and communications skills.
* Able to work with cross-functional teams and support less experienced team members.