Job Title: Experienced ASIC Digital Verification Engineer
We drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.
Responsibilities:
* Designing and implementing verification environments to ensure the correctness of Interface IP protocols.
* Creating and executing detailed test plans to verify complex ASIC designs.
* Developing and maintaining verification IP and testbenches using SystemVerilog and UVM.
* Collaborating with design and architecture teams to identify and fix bugs.
* Performing functional coverage analysis and driving coverage closure.
* Mentoring and guiding junior verification engineers in best practices and methodologies.
The Impact You Will Have:
* Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.
* Enhancing the robustness and efficiency of our verification processes and methodologies.
* Contributing to the successful launch of Interface IP products, impacting various industries.
* Driving innovation and excellence within the verification team.
* Improving the overall performance and functionality of Synopsys' IP offerings.
* Fostering a culture of continuous improvement and technical excellence.
Requirements:
* Extensive experience in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet.
* Proficiency in SystemVerilog and UVM methodologies.
* Strong understanding of digital design and verification concepts.
* Experience with simulation tools such as VCS, ModelSim, or similar.
* Excellent problem-solving skills and attention to detail.
What We Offer:
You will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges.