About the Role
We are seeking candidates for physical design, STA and power integrity engineering positions at our Cork, Ireland location.
You will be part of a global team that drives and executes on all phases of the complete physical implementation for next-generation premium-tier Snapdragon SOCs in bleeding-edge technologies.
Responsibilities:
* Work on physical implementation from floorplan to GDS for high-speed complex designs with aggressive PPA targets.
* Contribute to research of innovative methodologies for pushing PPA limits in physical design, including development of scripts and flows.
* Collaborate with cross-functional teams on understanding design in context of physical implementation, timing closure, and power optimization.
* Demonstrate good understanding of industry trends and innovations in physical design to ensure solutions and deliverables align with best practices.
* Perform complex analyses using statistics and data predictions to track benchmarks and identify issues or areas for improvement.
* Work across teams to align on important areas of PPA improvement and ensure targets are met; ensure designs are innovative and compatible with highest standards.
Requirements:
* 4+ years of relevant experience in Physical Design.
* Knowledge of entire PD flow from netlist to GDS (Floorplanning, Power planning, Placement/CTS/Routing and corresponding optimization steps).
* Good experience and knowledge of tools for physical design implementation in advanced technologies nodes (10nm and below).
* Excellent understanding of STA and timing closure methodologies, including impact on congestion/routing/power.
* Good understanding of power analysis and power integrity analysis.
* Understanding of Physical Verification and DRC closure.
* Expert in automation skills using Perl and TCL and able to develop/support flows related to physical design.
* Good communication skills and ability & desire to work in a cross-functional team environment.
What We Offer:
* Salary, stock, and performance-related bonus.
* Maternity/Paternity Leave.
* Employee stock purchase scheme.
* Matching pension scheme.
* Education Assistance.
* Relocation and immigration support (if needed).
* Life, Medical, Income, and Travel Insurance.
* Subsidised memberships for physical and mental well-being.
* Bicycle purchase scheme.
* Employee-run clubs, including running, football, chess, badminton, and many more.
Qualifications:
* Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
* OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
* OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.