Job Overview
Our client develops leading edge Intellectual Property (IP) for various High-Tech Markets. Their IP solutions enable customers to tackle IP-to-SoC development in a system context, allowing them to focus on product differentiation and reducing time to volume.
Main Responsibilities
* Architecture of Verification Environments for complex IP such as Ethernet, CXL, Storage.
* Development of UVM-SV Scoreboards for self-checking regressions.
* Development of Functional Coverage as part of Metric Driven Verification Environments.
* Development of SystemVerilog Assertions for use in Formal and Simulation Environments.
* Definition and Management of Verification Plans (vPlans) using Cadence vManager tools.
* Creation and Management of Automated Regression Environments, e.g. Jenkins.
* Participation in Technical Review Meetings and Checklist Reviews as part of ISO-9001.
* Closing Collaboration with Design Engineers to debug complex test scenarios.
* Improving quality and efficiency and helping refine the development process for greater productivity of the team through automation and improved methods.
* Work across disciplines with Design, Support, Delivery, Application Engineers, PHY team, etc.
Qualifications
* Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline.
* 10-15 years' experience in microelectronics/EDA industry.
* Experience of SystemVerilog Constrained Random Verification essential.
* Experience of Metric Driven Verification (MDV) essential.
* Excellent oral and written English essential.
* Self-motivated with excellent planning, interpersonal, and communication skills.
Additional Skills/Preferences
* Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis preferred.
* Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred.
* AXI and/or CHI-E experience is highly desirable.