Responsibilities
in Design and Verification
1. Produce high quality Analog/RF systems/sub-systems using industry best practice methods for design, verification and test according to project plans.
2. Generate, document and verify behavioural models of analogue and analogue-mixed-signal blocks (e.g. using VerilogA/AMS, SystemVerilog-RNM, Wreal) and ensure they are optimised and kept up to date.
3. Write verification plans and create automated test benches.
4. Design and verify RF/Analog blocks/subsystems (e.g. LNA, PA, VCO, PLL, mixers, bandgaps, LDO, DC-DC, ADC, DAC, etc), up to an operating frequency of 20GHz, using industry standard tools and design flows.
5. Work closely with IC Layout Design Engineers to optimise design and layout.
6. Ensure that designs follow industry best practice design flows, verification techniques, Design For Test (DFT), isolation, power optimisation etc.
7. Host design/verification reviews.
8. Support lab evaluation, characterisation and test.
Interpersonal
9. Interact with other engineers in the mixed signal, and digital/systems/SW/apps/test teams to ensure products are delivered to meet or exceed specifications on time and in budget.
10. Good team player with good interpersonal skills but can work independently on complex tasks.
11. Help drive continuous productivity improvements through improved work methodologies, efficient tool use and good documentation.
12. Mentor junior employees and interns.
Qualifications
13. Minimum Masters of Science in Electronic Engineering or related field.
14. 10+ years relevant industrial experience required.
15. Excellent working knowledge of the Cadence Virtuoso design environment.
16. Detailed design experience of analog/mixed-signal circuits on advanced CMOS nodes (40nm and lower).
17. Clear and concise communication and presentation skills.
18. Experience with getting full chip designs to product release preferred.
19. Experience with high frequency RF designs is desired.
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