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Team Lead | Semiconductor, Embedded Systems, CPU, GPU
Opportunity to work for a globally leading semiconductor, wireless and chip company at their growing R&D center in Ireland as part of their Timing / STA teams.
Responsibilities
* Involved in aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.
* Define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.
* Utilises tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.
Requirements
* Very experienced with timing related activities and responsibilities such as library, LVF, AOCV/POCV/SOCV.
* Good understanding of library characterisation process and flow with hands on experience on standard cell library characterisation.
* Proven knowledge of latest technologies nodes and practices in physical design including Place and Routs (P&R) and Static timing analysis (STA) sign-off.
* Be willing to learn and involve in developing and validating new methodologies.
* Experience with CAD tools including correlation between different timing sign-off tools vs. Spice simulation across different metrics such as timing, noise, monte-carlo, etc.
* Working knowledge of Spice extraction, modelling and aging reliability model for latest technology nodes.
If this is of interest then please get in touch and we can discuss: lg@eu-recruit.com
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Seniority level
* Mid-Senior level
Employment type
* Full-time
Job function
* Design, Engineering, and Information Technology
* Industries: Computer Hardware Manufacturing
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