Job Overview
Our client is a leading provider of Intellectual Property (IP) solutions for the high-tech market. Their IP enables customers to focus on product differentiation and reduce time to volume.
This role offers an opportunity to join a development team designing state-of-the-art DDR memory controllers for various applications, including data centers, edge computing, automotive, and artificial intelligence.
Key Responsibilities
* Architecture of Verification Environments for complex IP such as Ethernet, CXL, and Storage
* Development of UVM-SV Scoreboards for self-checking regressions
* Development of Functional Coverage as part of Metric Driven Verification Environments
* Development of SystemVerilog Assertions for use in Formal and Simulation Environments
* Definition and Management of Verification Plans using Cadence vManager tools
* Creation and Management of Automated Regression Environments
* Participation in Technical Review Meetings and Checklist Reviews
* Closure Collaboration with Design Engineers to debug complex test scenarios
* Improvement of quality and efficiency and help refine development process through automation and improved methods
* Work across disciplines with Design, Support, Delivery, Application Engineers, PHY team, etc.
Required Qualifications
* Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline
* 10-15 years' experience in microelectronics/EDA industry
* Experience of SystemVerilog Constrained Random Verification essential
* Experience of Metric Driven Verification (MDV) essential
* Excellent oral and written English essential
* Self-motivated with excellent planning, interpersonal, and communication skills
Additional Skills/Preferences
* Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis preferred
* Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred
* AXI and/or CHI-E experience is highly desirable