We are seeking a highly skilled R&D Senior Staff Design Engineer to join our team responsible for DDR/HBM PHY architecture.
Job Summary
This is a senior-level engineering position that involves planning and executing the design of next-generation DDR and HBM PHYs in the Synopsys IP portfolio. The successful candidate will work closely with senior architects, designers, and engineers to create leading-edge products.
About the Role
In this role, you will be responsible for understanding standard specifications, evaluating ideas, drafting specifications, and enabling a larger team of design engineers to bring new ideas into silicon. You will leverage your expertise in computer architecture, mixed-signal design, off-chip signaling, RTL development, design-for-test, and logical verification to create innovative solutions.
Key Responsibilities
* Understand marketing requirements, customer desires, and standard specifications and translate them into product design features and functions.
* Generate functional descriptions for products, creating specifications describing interface components, operation, structure, and behavioral parameters.
* Develop models representing performance features of interface design sub-components.
* Solve design execution problems tied to product definition.
* Perform feasibility studies through evaluation of trial designs.
* Document results, conclusions, and technical insights into performance, power, area, and functional parameters.
* Interact and communicate with design teams performing digital design and verification, analog circuit design and verification, and layout design.
* Support customers in their implementation of products.
Requirements
* A minimum of 8+ years of related experience or an advanced degree with 6+ years of related experience.
* Expertise in high-speed interface principles, such as mixed-signal design and off-chip signaling.
* Strong skills in generating and supporting documentation through written specifications and communicating those specifications within a design team and to external customers.
* Well-versed in RTL logic design, simulation, test planning, and verification of complex integrated circuit components.
* Knowledgeable in design-for-test, timing analysis, power analysis, behavioral modeling, and synthesis constraints.
* Able to work across a multi-site team to communicate ideas, understand problems, and find solutions to create a leading-edge design.
* Skilled in troubleshooting and debug of mixed-signal interfaces.
* Knowledge in DDR protocols and JEDEC spec is a plus.
* Experience with GenAI in the design process is a plus.
* Able to work autonomously with high-level guidance.
Estimated Salary: $150,000 - $200,000 per year
About Us
We are a leading provider of electronic design automation (EDA) software and IP solutions. Our company is committed to innovation and excellence in all aspects of our business.