ASIC Design Verification Engineers of varying seniorities - Amazing Salary Packages
A global leading chip company, at the forefront of technology innovation, is seeking a highly motivated and experienced ASIC Design Verification Engineers of varying seniorities to join our growing teams in Cork. They are pushing the boundaries of what's possible, enabling next-generation experiences and driving communication and data processing transformation to create a smarter, connected future. This technology-focused role offers the opportunity to participate in a broad range of sensor systems engineering activities.
* This role would be an on-site role with 1 day a week remote working.
* Providing VISA for candidates 4 years post education. + Relocation assistance!
* Based in Cork - Ireland
Responsibilities:
* Deploy industry-leading verification methodologies such as UVM and Formal Verification.
* Develop testbenches and verification components, including UVCs, C models, and reusable verification environments.
* Verify sensor algorithm RTL for ASIC tapeout quality delivery.
* Develop test plans based on design documents and interaction with design/systems engineers.
* Implement C model integration within the UVM framework.
* Write SystemVerilog assertions.
* Debug, verify, optimize, and perform bit-exact matching with test vectors.
* Analyze coverage data and collaborate with design teams to address coverage holes.
* Develop and augment frameworks for running regressions.
* Debug regression failures with design/systems teams.
* Automate workflows and improve team efficiency using Python.
* Participate in all project reviews.
* Support software and other teams with debug.
* Create and maintain documentation.
Qualifications:
* Bachelor's degree in Science, Engineering, or a related field.
* 3+ years of experience in ASIC design verification, UVM-based functional verification, or a related field.
* Experience with constrained-random verification environments and UVM flow build-up, including Coverage-Driven verification methodology.
* Proficiency in SystemVerilog Assertions.
* Experience debugging test failures and reporting verification results to achieve coverage goals.
* Extensive experience using RTL simulation tools.
* Strong UVM, SystemVerilog, and Perl/Python shell-scripting skills.
* Familiarity with C/C++.
* Strong analytical skills and the ability to thrive in a dynamic, fast-paced team environment.
* Excellent written and verbal communication skills.
* Strong interpersonal skills and a collaborative team player.
Preferred Qualifications:
* Experience using formal verification tools (e.g., Jasper, VC_Formal).
* Experience with SystemC and Matlab.
* Experience with gate-level simulation debug and power extraction tools.
Keywords: RTL, ASIC, Power, SystemC, ECO, MBIST, Architecture, Design, Design Verification, Jasper, VC Formal, Catapult, Stratus, Sensors, Accelerometer, Gyroscope, Magnetometer, IMU, Embedded Systems, Medical Sensors.
Seniority level
Mid-Senior level
Employment type
Full-time
Job function
Engineering and Design
Industries
Semiconductor Manufacturing
#J-18808-Ljbffr