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Responsibilities
* Implement verification for block level, subsystem and SoC level designs using advanced verification methodologies to meet quality and schedule goals.
* Work with system architects and RTL designers to develop verification requirements and test plans based on specifications.
* Analyse and debug simulation failures.
* Create, track, and close bugs in bug tracking tool.
* Analyse code coverage and functional coverage reports.
* Perform regression analysis.
* Develop, maintain and publish verification specifications.
Qualifications
* BSEE/BSc (MEng preferred) as well as at least 9 years relevant work experience.
* Fluent in System Verilog UVM and SVA.
* Excellent debugging and problem-solving skills.
* Familiarity with Metric Driven Verification methodology.
* Experience in writing test plans and creating directed and random test cases.
* Working knowledge of Linux operating system.
* Embedded C experience considered an advantage.
* Experience with Synopsys tool suite is an advantage.
* Preferably knowledge of AMBA and wired/wireless protocols.
* Excellent written and oral communication skills.
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