Job Title:
Power Management Verification Engineer
About the Role:
We are seeking strong DV engineers to verify high performance and low power CPUs in Bangalore.
Key Responsibilities:
* Responsible for power management verification including Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.
* Work closely with design/verification teams within CPU to develop comprehensive test plan.
* Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus.
* Verify power intent through use of methodologies like UPF.
* Work closely with system architects, software teams and Soc team to validate system use cases.
* Work closely with emulation team to enable verification on emulators and FPGA platforms.
* Debug and triage failures in simulation, emulation and/or Silicon.
Requirements:
* Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
* OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
* OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
* BE/BTech degree in CS/EE with 3+ years' experience.
* Experience in power management verification.
* Implementation of assembly and C language embedded firmware.
* Experience in C/C++, scripting languages, Verilog/system Verilog.
* Strong understanding of power management features in CPUs and CPU based Socs.
* Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.
Preferred Requirements:
* Good Understanding of CPU architectures and CPU micro-architectures.
* In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture.
* Experience with advanced verification techniques such as formal and assertions is a plus.
* Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus.