Job Description
The Client, a Leading Multinational Semiconductor Telecom Organisation, Requires a Contract Senior RTL Design Engineer for a 6-Month Daily Rate Role.
This is a Remote Working Position Requiring a Time Difference of No More Than +2 Hours from Ireland.
Key Responsibilities:
* Translate Signal Processing Algorithms into Fully Synthesizable RTL Code
* Propose a Micro-Architecture and Verilog Coding for an Existing IP
* Develop a Verified Block Allowing a Die Size Reduction by 2 to 4
* Integrate the New Block into Different Wi-Fi IP Versions
* Support the UVM Team for Debugging
Requirements:
* Engineering Degree in Computer Sciences
* 8+ Years of Experience in Digital Design
* Ability to Follow a Design Flow (RTL, Testbench, Code Coverage, Synthesis, Formal Verification, Gate Level Simulation)
* Highly Experienced in Verilog
* Strong Background in Communication Theory and Digital Signal Processing, Particularly Experience with OFDM and MIMO Technologies
* Familiar with Matlab
* Strong Written Communication Skills in the Form of Functional, Design, and Test Plan Documentation
* Excellent Communications and Interpersonal Skills in English