Principal Verification Engineer - UVM / SystemVerilogCome and be part of a global expanding company that's pivotal in the world of hardware and software design.As a Principal Verification Engineer, you will be architecting verification environments for IPs such as Storage, Ethernet, Memory, etc., and as a Principal, driving this forwards. You will also be part of technical review meetings and checklist reviews.The role is a permanent, full-time position and is based in Cork, Ireland, so it will involve relocation if you're not based here. You must be on-site a minimum of 3 days per week.Salaries will consist of a base salary + 10% bonus + RSUs + lunch allowance + relocation support + other benefits, depending on experience.For this Principal Verification Engineer position, I'm interested in speaking to people with the following:Strong experience in verificationExperience with UVMExperience with SystemVerilogSome leadership/guidance experienceExperience of metric-driven verification is essentialMust have the right to work in Ireland without sponsorshipI welcome your application if you'd like to find out more and if you know someone it would suit, we offer a fantastic referral scheme which I would be happy to discuss.Keywords: Semiconductors / Verification / Metric Driven Verification / UVM / System Verilog / Memory / DDR / Ethernet
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