Principal Verification Engineer (DDR/Memory)
About the Role
We are seeking a Principal Verification Engineer to join our team in Cork, Ireland. The ideal candidate will have a strong background in verification of complex IP such as DDR memory controllers.
Key Responsibilities
* Design and implement verification environments for complex IP
* Develop UVM-SV scoreboards for self-checking regressions
* Create and manage automated regression environments
* Participate in technical review meetings and checklist reviews
* Collaborate with design engineers to debug complex test scenarios
Requirements
* Degree in Electrical/Electronic Engineering or related discipline
* 10-15 years' experience in microelectronics/EDA industry
* Experience with System Verilog Constrained Random Verification
* Excellent oral and written communication skills
About Us
Cadence is a leading provider of Intellectual Property solutions for the biggest names in the technology industry. We develop state-of-the-art DDR memory controllers for a wide range of applications including Datacenter, Edge computing, Automotive, and AI.