The Digital Design Engineer will be responsible for the design and verification of our Video IP cores. Part of a team of top-class industry video experts, you will develop high-performance Video compression and decompression IP cores in RTL supporting all video standards including HEVC, AV1, and VVC.
Qualifications
BEng, MEng, or MS in Electronics Engineering or related discipline. The ideal candidate has knowledge of Front-End design for ASIC, video processing/coding, or signal processing, fluent English communication skills, and must be a great team player.
Skills/Experience
1. Verilog (and/or VHDL) language proficiency.
2. Excellent skills in CAD tools and ASIC design flows (modeling, design, simulation, synthesis, verification, etc.).
3. Knowledge of C/C++, scripting languages, and optimization of architectures and micro-architectures at HW/RTL level is required.
4. Understanding of video compression/decoding algorithms (for example: H.264, H.265) is a plus.
#J-18808-Ljbffr