Job Title: Principal Verification Engineer (Memory)
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This is an opportunity to join a development team designing state-of-the-art DDR memory controllers for various applications, including datacenter, edge computing, automotive, and AI.
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The Cadence Silicon Solutions Group develops leading-edge intellectual property for high-tech markets. Our IP solutions enable customers to tackle IP-to-SoC development in a system context, allowing them to focus on product differentiation and reduce time to volume.
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The Principal Verification Engineer will work with an experienced controller IP team based in Cork, part of established controller development sites in Europe, US, and India.
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Key Responsibilities:
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* Architecture of verification environments for complex IP such as Ethernet, CXL, and Storage
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* Development of UVM-SV scoreboards for self-checking regressions
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* Development of functional coverage as part of metric-driven verification environments
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* Development of SystemVerilog assertions for use in formal and simulation environments
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* Definition and management of verification plans using Cadence vManager tools
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* Creation and management of automated regression environments
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* Participation in technical review meetings and checklist reviews
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* Closely collaborating with design engineers to debug complex test scenarios
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* Improving quality and efficiency by automating processes and refining the development process
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Requirements:
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* Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline
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* 10-15 years' experience in microelectronics/EDA industry
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* Experience with System Verilog constrained random verification
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* Experience with metric-driven verification
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* Excellent oral and written English skills
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* Self-motivated with excellent planning, interpersonal, and communication skills
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Desirable Skills:
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* Experience with front-end design tools, including lint, synthesis, and CDC analysis
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* Quality processes, such as ISO-9001 & ISO-26262
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* AXI and/or CHI-E experience
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