Responsibilities Layout Design & Verification Work with Analog/RF Design Engineers to create and optimise the design and layout of complex RF and mixed signal blocks Produce highest quality RF/Analog systems using industry best practice methods for layout and physical verification Full top level / SOC ownership and block level ownership as well as full top-level floor planning Detailed verification and debug from block level to top level Lead and document layout design reviews Interpersonal Work together with other engineers in the RF/Analog design team to ensure designs are delivered to specifications and on time Good team player but can work independently on complex tasks Mentor junior layout engineers and guide layout contractors Help drive continuous productivity improvements through improved work methodologies, efficient tool use and good documentation Qualifications Minimum of Bachelor's degree in Electronic Engineering or related field 10+ years relevant industrial experience required Excellent working knowledge of the Cadence Virtuoso suite and Calibre verification tools Detailed experience of analog/mixed-signal layout on advanced CMOS nodes (40nm and lower) Must understand issues of LDE, isolation, matching, parasitic effects, EM and IR drop Verification checks (DRC/LVS) Strong analytical and debug skills Experience with high frequency RF designs Experience writing Skill code a plus