Associate Consultant at USA Tech Recruitment
GPU Design Implementation Engineer
About the role
As a member of the Graphics team, the successful applicant will help integrate, implement, and develop state-of-the-art GPU cores and will be working closely with the graphics microarchitecture and physical design teams. The successful candidate will possess an in-depth understanding of ASIC design flow and the challenges posed by advanced deep sub-micron technologies.
The Design Implementation Engineer will work in our GPU team and will be responsible for managing all aspects of front-end implementation design challenges and methodology. The role will also include working with execution-driven teams for tape-outs by supporting new methodologies and new flows required to address better QoR like performance, power, and area.
Responsibilities
* RTL to GDS2 flow, tools, and methodologies such as synthesis, static timing analysis, formal verification, physical design, and ECO generation/verification
* Implementation and delivery of GPU cores from RTL to GDSII
* Identify areas for flow and process improvements
* RTL synthesis using physically aware tools
* Formal Verification using industry-standard tools for RTL-netlist and netlist-netlist checks
* Close design timing by running static timing analysis and constraint development
* Generate and verify ECOs for functional and timing fixes, working closely with the physical design team
* Low Power synthesis flows for multiple corners
Skills and Experience we would love to see
* Knowledge and experience of graphics design and development
* Proficient in Perl, TCL, and shell scripting
* Hands-on experience with front-end EDA tools such as Synopsys Next Generation tools, Conformal LEC, Synopsys Formality, and Synopsys PrimeTime
* Familiar with the latest EDA tools for synthesis, logic equivalence checking, timing analysis, physical design
* Able to problem-solve complex, unique, and detailed issues
Minimum Qualifications
* Bachelor's degree in Engineering, Science, or a closely related field
* 6+ months of experience with digital design and RTL development
* 6+ months of experience with synthesis, static timing, timing closure, constraints, and formal verification
Seniority level: Mid-Senior level
Employment type: Full-time
Job function: Engineering and Design
Industries: Semiconductor Manufacturing, Computer Hardware Manufacturing, and Computers and Electronics Manufacturing
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