Principal Design Engineer (DDR/Memory)
This is an opportunity to join a development team designing state-of-the-art DDR memory controllers to be used in a wide range of applications including Datacenter, Edge computing, Automotive, and AI.
Key Responsibilities:
* Architect solutions for the latest DDR controller features and customer requirements.
* Design RTL in a highly configurable and automated environment.
* Work in small project teams with cross-functional disciplines.
* Utilize Cadence's Design Automation flow and IP development tools.
* Develop high speed circuits and low power features.
* Improve quality and efficiency through automation and improved methods.
Requirements:
* Bachelor's or Master's degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline.
* 10+ years' experience in microelectronics/EDA industry.
* Experience of Verilog RTL Design essential.
* Excellent oral and written English essential.
* Self-motivated with excellent planning, interpersonal, and communication skills.
Preferred Skills:
* Experience of AMBA protocols such as CHI, AXI, AHB & APB preferred.
* Experience of SystemVerilog for design preferred.