Company:
Qualcomm India Private Limited
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world-class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications:
1. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
2. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
3. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
Job Role:
1. Familiar with Physical Design Life cycle of chip development, especially Floorplanning and PnR.
2. Hands on PD execution at block/SoC level along with PPA improvements.
3. Strong understanding of the technology and PD Flow Methodology enablement.
4. Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies (area/power/performance/convergence), develop plans and deploy/support them.
5. Provide tool support and issue debugging services to physical design team engineers across various sites.
6. Develop and maintain 3rd party tool integration and productivity enhancement routines.
7. Understand advance tech PNR and STA concepts and methodologies and work closely with EDA vendors to deploy solutions.
Skill Set:
1. Strong programming experience & Proficiency in Python/Tcl/C++.
2. Understand physical design flows using Innovus/fc/icc2 tools.
3. Knowledge of one of Encounter/Innovus or FC (or other equivalent PNR tool) is mandatory.
4. Basic understanding of Timing/Formal verification/Physical verification/extraction are desired.
5. Ability to ramp-up in new areas, be a good team player and excellent communication skills desired.
Experience:
3-5 years of experience with the Place-and-route and timing closer and power analysis environment is required.
Niche Skills:
Handling support tools like Encounter/Innovus/edi/fc/Icc2 (or other equivalent PNR tool). One or more of the above is mandatory.
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