Job Title:
Principal Design Engineer (DDR/Memory)
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Location:
Cork
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Reports to:
Design Engineering Director
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Job Overview:
The Cadence Silicon Solutions Group develops leading edge Intellectual Property for various High-Tech Markets. This is an opportunity to join a development team designing state-of-the-art DDR memory controllers used in Datacenter, Edge computing, Automotive, and AI applications.
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Key Responsibilities:
* Architect solutions for the latest DDR controller features and customer requirements.
* Design RTL in a highly configurable and automated environment.
* Work in small project teams.
* Collaborate with cross-disciplinary teams including Design Verification, Support, Delivery, Application Engineers, PHY design team, etc.
* Utilize Cadence's Design Automation flow and IP development tools.
* Develop high-speed circuits and low-power features.
* Improve quality and efficiency by refining development processes through automation and improved methods.
* Participate in an engineering team to advance our product.
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Requirements:
* Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline.
* 10+ years' experience in microelectronics/EDA industry.
* Experience of Verilog RTL Design essential.
* Experience of Metric Driven Verification (MDV) essential.
* Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential.
* Experience of SoC Architecture and Development essential.
* Experience of Technical Team leadership essential.
* Excellent oral and written English essential.
* Self-motivated with excellent planning, interpersonal, and communication skills.
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Preferred Skills:
* Experience of AMBA protocols such as CHI, AXI, AHB & APB preferred.
* Experience of SystemVerilog for design preferred.
* Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred.
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Estimated Salary:
$120,000 - $180,000 per year, depending on location and experience.