Job Title: ASIC Digital Verification Engineer
We drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.
About the Role:
A passionate and detail-oriented ASIC Digital Verification Engineer ready to make an impactful contribution. You bring a strong foundation in digital design and verification, with a deep understanding of RTL design, simulation, and debugging.
Key Responsibilities:
* Developing and implementing verification plans for complex ASIC designs.
* Creating and maintaining testbenches using SystemVerilog/UVM.
* Executing simulation and debugging of RTL designs to ensure functionality and performance.
* Collaborating with design and architecture teams to identify and resolve bugs.
* Automating verification processes to enhance efficiency and coverage.
* Conducting code reviews and providing feedback to improve verification quality.
* Analyzing verification results and generating comprehensive reports.
* Participating in design reviews and contributing to the overall design verification strategy.
* Performing regression testing and analyzing coverage metrics to ensure thorough verification.
The Impact You Will Have:
* Ensuring the delivery of high-quality, reliable silicon IP that meet performance and functionality requirements.
* Reducing time-to-market by identifying and resolving design issues early in the verification process.
* Enhancing the efficiency of the verification process through automation and best practices.
* Contributing to the development of cutting-edge technology that powers advanced applications like AI, automotive, and IoT.
* Collaborating with cross-functional teams to drive innovation and continuous improvement.
* Supporting the scalability and robustness of Synopsys' verification methodologies and tools.
* Driving the adoption of best practices in verification across the organization.
* Enhancing the reliability and performance of Synopsys' products, leading to increased customer satisfaction and market share.
Requirements:
* B.Sc./M.Sc. in Computer Engineering/Electrical Engineering/Communication Engineering
* 8+ years(BS) / 6+ years(MS) of ASIC design verification and have knowledge about System Verilog and UVM, Object oriented coding, and verification
* Experience with RTL simulation tools such as VCS, NCSim, or Questa.
* Solid understanding of digital design concepts and verification methodologies.
* Proficiency in scripting languages like Python, Perl, or Tcl for automation.
* Familiarity with version control systems like Git or Perforce.
* Excellent debugging and problem-solving skills.
* Strong analytical skills and attention to detail.
* Experience with coverage-driven verification and formal verification techniques.
* Knowledge of industry-standard protocols and interfaces such as PCIe, CXL, AMBA.
* Ability to work in a fast-paced environment and manage multiple priorities effectively.
What We Offer:
A comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.
Who We Are:
Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.