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Staff Level Digital Design Engineer Role
The AMD SerDes team in Ireland is hiring a Staff level digital design engineer to work on the development of digital designs for complex mixed-signal ICs in the latest CMOS FinFET processes.
Responsibilities:
* RTL implementation of algorithms for clock and data recovery, adaptive digital control, and DSP.
* Communication with the architecture team to understand proposed algorithms and provide feedback regarding design implementation.
* Digital design verification to ensure basic design functionality prior to hand-off of the design to the verification team.
* Design verification using standard industry tools for HDL checking (e.g., CDC, RDC, Lint).
* Support of the verification team in the debug of identified issues.
* Assist with silicon bring-up and debug.
* Creation of clear design specifications and implementation documentation.
Preferred Experience:
1. Extensive experience in RTL design methodologies, specification development, and design implementation.
2. Familiarity with RTL design using a HDL such as Verilog or VHDL, with a preference for Verilog.
3. Experience in modern digital ASIC methodologies, including verification, STA, signal integrity, DFT, synthesis, physical implementation.
4.