About the Role
We offer flexible work options tailored to our employees' needs. This includes a combination of working from home and working in our brand new, state-of-the-art office in Penrose Dock, Cork.
Responsibilities:
* Deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification
* Developing Testbenches and Verification Components such as UVCs, C models, and Vertical/Horizontal re-usable Verification Environments.
* Verifying sensor algorithms RTL for ASIC tapeout quality delivery
* Test plan development based on Design documents and interaction with design/systems engineers
* Implementing C model integration within UVM framework.
* Writing System Verilog assertions
* Debugging, verifying, optimizing, and bit-exact matching with test vectors
* Analyzing coverage data and working with Design teams to address coverage holes
* Develop/augment framework for running regressions
* Debugging regression failures with design/Systems teams
* Support integration of design in higher-level subsystem including test planning, test vector delivery, and debug of test vectors at the integration level
* Python automation for improving workflows and team efficiency
* Participate in all project reviews
* Supporting software and other teams with debug
* Documentation
Requirements:
* Bachelor's degree in Science, Engineering, or related field
* 3+ years ASIC design verification, UVM-based functional verification, or related work experience
* Experience using formal verification tools like Jasper or VC_Formal is a plus
* Experience with System C and Matlab are a plus
* Gate level Simulation debug and usage of power extraction tools is a plus
* Experienced with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodology
* Experienced with Assertions like System Verilog Assertions
* Experience with debugging test failures and report verification result to achieve the expected code/functional/line coverage goals
* Extensive usage of RTL simulation tools
* UVM, System Verilog, Perl/Python shell-scripting skills required
* Familiarity with C/C++
* Strong analytical skills and ability to work in a dynamic and fast-paced team environment
* Excellent written and verbal skills
* Strong interpersonal skills and a good team player
What We Offer:
* Apart from working in an open, relaxed, and collaborative space, you will enjoy:
* Salary, stock, and performance-related bonus
* Maternity/Paternity Leave
* Employee stock purchase scheme
* Matching pension scheme
* Education Assistance
* Relocation and immigration support (if needed)
* Life, Medical, Income, and Travel Insurance
* Subsidised memberships for physical and mental well-being
* Bicycle purchase scheme
* Employee-run clubs, including running, football, chess, badminton, and many more