At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Job Title: Lead Analog Layout Design Engineer (SERDES)Location: Cork Reports to: Group DirectorJob Overview:The Lead Analog Layout Design Engineer will take a senior role on the PMA custom layout design team as part of a SERDES Product Team located at Cork, Ireland.Job Responsibilities:Design of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g. 3nm FinFET CMOS)Design quality layouts of analog/mixed-signal circuit blocks, working in collaboration with circuit designersResponsibilities include all facets of the back-end flow, from initial floor planning through detailed layout and final verification of conformance to foundry design rulesWork with Technical Team Leads in the areas of blocks layout design and PHY top levelsMentor Junior Layout Design Engineers when the project need arisesWork with global teams (US, west coast and east coast), which work in different time-zonesJob Qualifications:Candidate’s background should include a minimum of 4 years of experience in CMOS SERDES or high-speed I/O IC layout design and developmentExcellent layout design experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage RegulatorsImplementing high speed and high accuracy cells, blocks and IP blocks in a timely fashion with high quality and efficiencyAssist with the architecture and implementation of complete PHY gds with integration of PMA, PCS hierarchies and optimized clock and power distribution strategiesWorking with custom layout designers from groups all over the world to build high quality IP and test chipsWorking with circuit designers and project managers from groups all over the world to understand their technical and schedule needsExcellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environmentBEng, MEng or PhDAdditional Skills/Preferences: Cadence tool experience and design experience at >10Gbps and in 10%We’re doing work that matters. Help us solve what others can’t.