Physical Design Engineer | Power, Performance, and Area
We are seeking a Physical Design Engineer to work with one of the largest and most well-known semiconductor & graphics companies in the world and work on techniques for low power designs and UPF/CPF flows.
Are you a skilled Physical Design Engineer ready to take on challenging projects? We're seeking a talented individual to join our team and contribute to the development of cutting-edge semiconductor solutions.
Key Responsibilities:
* Drive the full physical design flow, from netlist to GDS, including:
Floor planning, Power planning, Placement & optimization, Clock tree synthesis (CTS), Routing, Static timing analysis (STA), Post-route optimization, Design rule check (DRC) closure.
* Collaborate with cross-functional teams to ensure timely and high-quality deliverables.
* Develop and implement innovative low-power design techniques, leveraging UPF/CPF flows.
* Master timing closure methodologies, including Primetime STA, and effectively address timing ECOs.
* Optimize power grid structures, clock trees, and low-power reduction strategies.
* Proactively identify and resolve signal integrity and timing closure challenges like OCV, AOCV, and statistical timing.
* Utilize physical verification, IR drop analysis, and formal verification tools to ensure design integrity.
* Automate design flows using Perl/Python and TCL scripting to improve efficiency and productivity.
Qualifications:
* Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
* 5+ years of hands-on experience in ASIC physical design.
* In-depth knowledge of industry-standard physical design tools from Synopsys (ICC2/Fusion Compiler) or Cadence (Innovus).
* Proficiency in synthesis tools like Synopsys DC/Fusion Compiler or Cadence Genus.
* Strong understanding of advanced process node technologies.
#J-18808-Ljbffr