Press Tab to Move to Skip to Content Link
Select how often (in days) to receive an alert:
ASIC Layout LeadJob Type: Full-Time
Location: Ireland - Dublin, IE
Requisition ID: 7492
Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible.
We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges.
Qorvo serves diverse high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense.
Visit www.qorvo.com to learn how our diverse and innovative team is helping connect, protect and power our planet.
Summary As ASIC Layout Lead, you will work as part of a cross-functional team to deliver the next generation UWB products from concept to volume production.
Responsibilities Layout Design & Verification Work with Analog/RF Design Engineers to create and optimise the design and layout of complex RF and mixed signal blocksProduce highest quality RF/Analog systems using industry best practice methods for layout and physical verificationFull top level / SOC ownership and block level ownership as well as full top-level floor planningDetailed verification and debug from block level to top levelLead and document layout design reviewsInterpersonal Work together with other engineers in the RF/Analog design team to ensure designs are delivered to specifications and on timeGood team player but can work independently on complex tasksMentor junior layout engineers and guide layout contractorsHelp drive continuous productivity improvements through improved work methodologies, efficient tool use and good documentationQualifications Minimum of Bachelor's degree in Electronic Engineering or related field10+ years relevant industrial experience requiredExcellent working knowledge of the Cadence Virtuoso suite and Calibre verification toolsDetailed experience of analog/mixed-signal layout on advanced CMOS nodes (40nm and lower)Must understand issues of LDE, isolation, matching, parasitic effects, EM and IR dropStrong analytical and debug skillsExperience with high frequency RF designsExperience writing Skill code a plusMAKE A DIFFERENCE AT QORVO
We are Qorvo.
We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure markets – we are a place to innovate and shape the future of wireless communications.
It starts with our employees.
As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next.
Explore the possibilities with us.
#J-18808-Ljbffr