Job Title: Design Verification Engineer (DV Engineer role)
Contract: 6 months in Cork, Ireland
Key Responsibilities:
* Deploy verification methodologies such as UVM and Formal Verification.
* Develop testbenches and verification components like UVCs, C models, and reusable verification environments.
* Create test plans based on design documents and collaborate with design/systems engineers.
* Write and debug SystemVerilog assertions.
* Analyze coverage data and work with design teams to address coverage holes.
* Develop or augment frameworks for running regressions.
* Run and debug power-aware simulations using UPF.
* Debug regression failures with design/systems teams.
* Automate workflows and improve team efficiency using Python/Perl.
* Support software and other teams with debugging.
* Maintain documentation.
Required Experience:
* Experience in designing and verifying SoCs and SoC methodologies for complex units on SoCs using industry-standard tools and technologies.
* Proficiency in developing unit and subsystem-level testbenches using SV/UVM methodology.
* Familiarity with constrained random and metrics-driven verification.
* Experience with C model integration and scoreboarding.
* Verification of FW code integration.
* Knowledge of AMBA protocols and bus interconnect functional and formal verification, along with coverage closure.
* Experience with power-aware verification and clock domain crossing verification.
* Experience in debugging test failures.
* Strong knowledge of verification planning, coverage analysis, pseudo-random, and constrained random techniques, assertion-based, and formal verification techniques using System Verilog.
* Experience with Verilog, C/C++, System C, TCL/Perl/Shell-Scripting.
* Strong analytical skills and ability to work in a dynamic and fast-paced team environment.
* Excellent communication skills.