Impactful Technology Leadership Opportunity
Cadence is a pioneering force in electronic design, building on over 30 years of computational software expertise. Our Intelligent System Design strategy enables the creation of software, hardware, and IP that bring design concepts to life.
Our customers are world-renowned companies delivering extraordinary electronic products from chips to boards to systems for dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health.
Job Title:
Principal Verification Engineer (SERDES)
Based at our R&D center of excellence in Cork, Ireland, the Cadence Serdes PHY team seeks ambitious analog designers to work on leading-edge Wireline technology at high data rates (112Gbps+) and on small technology nodes (e.g., 3nm).
The PHY team designs products for communication protocols such as PCIe (now at Gen 7) and UCIe (emerging Chiplets standard).
Job Responsibilities:
* Verification of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g., 3nm FinFET CMOS)
* Specification, Design, and Verification of High Speed PHY IP based on communication protocols (PCIe, Ethernet)
* Verification from initial concept/specification through final verification of conformance to customer specifications using Coverage metric Implementation, Tracking, and Closure
* Prototyping, Emulation, Customer delivery, and support
* Work with cross-functional teams ranging from architecture, all aspects of circuit design, Layout development, RTL design & Validation, Physical design & Test chip development
* Participate in technical leadership of the team in areas of digital design and verification, SERDES architectures
* Collaborate with global teams (US, West Coast, and East Coast), working in different time-zones
Qualifications:
* BEng, MEng, PhD, or equivalent
* Candidate's background should include a minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC design and development
* Working knowledge of common SERDES standards
* Wide experience with digital design and verification tools; RTL design using Verilog & verification with System Verilog and UVM
* Experience of Assertion-Based Formal Verification essential
* Experience of Front-end design tools covering LINT, Synthesis, & CDC Analysis
* Excellent problem-solving skills and ability to work cooperatively in a team environment
* Excellent communication and stakeholder management skills
Additional Skills/Preferences:
* Prior experience with post-Silicon validation & customer IP deployment of one or more Serial IO IPs/ complex Memory Interface IPs an added advantage
* Knowledge of PCIe, CXL protocols preferred
About Us:
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
Travel:
>10%